1. Field of Invention
The present invention relates to a method for etching a tantalum oxide (Ta.sub.2 O.sub.5) layer. More particularly, the present invention relates to a method of manufacturing dynamic random access memory (DRAM) that involves the sequential etching of a polysilicon layer and a tantalum oxide layer to form a pattern without having to switch etching stations.
2. Description of Related Art
A conventional dynamic random access memory (DRAM) structure at least includes a metal oxide semiconductor (MOS) transistor and a capacitor. The gate of the transistor is connected to a word line, and one of the source/drain regions is connected to a bit line BL. The other source/drain region is electrically connected to a capacitor, which in turn is connected to a ground. The capacitor structure in a DRAM can be regarded as a critical component in data storage. If the number of charges stored by a capacitor is large, the data bit stored in the capacitor is more stable. When the data bit stored in the capacitor is read out by an amplifier, a large capacitance is more capable of combating external noise.
In semiconductor manufacturing, a DRAM capacitor is formed by several steps. First, at least one transistor structure is formed on a semiconductor substrate, and then a storage node is formed above one of the source/drain regions of the transistor, thereby forming the lower electrode structure of a capacitor. Next, a tantalum oxide layer, a titanium nitride layer (TiN) and a polysilicon layer are formed sequentially over the lower electrode structure. The titanium nitride layer is formed above the tantalum oxide layer, and the two layers together constitute a composite dielectric layer for the capacitor. The polysilicon layer acts as an upper electrode structure of the capacitor. Finally, the tantalum oxide layer, the titanium nitride layer and the polysilicon layer are patterned to complete the DRAM capacitor structure.
FIG. 1 is a flow diagram showing the conventional manufacturing steps in patterning a multi-layered capacitor structure. First, step 10 represent the beginning of the operation where the multi-layered structure of the capacitor, including the lower electrode structure, the tantalum oxide layer, the titanium nitride layer and the polysilicon layer, has already been deposited. Next, step 12 is carried out by first performing a photolithographic operation, and then etching the polysilicon layer to form the upper electrode structure of the capacitor. Preferably, the etchant for etching the polysilicon layer is a gaseous mixture containing HBr/Cl.sub.2 /He--O.sub.2. Thereafter, a change in etching station is performed in step 14. The change is necessary because the etchant for etching the polysilicon layer is unsuitable for etching the tantalum oxide layer and the titanium nitride layer. Next, step 16 is carried out etching the titanium nitride layer and the tantalum oxide layer (TiN/Ta.sub.2 O.sub.5), thereby patterning the composite dielectric layer of the capacitor.
In patterning the tantalum oxide layer, the titanium nitride layer and the polysilicon layer, some problems often arise. The most severe problem occurs when etching of the polysilicon layer is finished, and the titanium nitride layer needs to be etched next. The etchant for etching the polysilicon layer is a gaseous mixture containing HBr/Cl.sub.2 /He--O.sub.2, which is unsuitable for etching titanium nitride. Therefore, both the processing station and the etchants need to be changed before subsequent etching of the titanium nitride layer and the tantalum oxide can be performed. This switchover of processing station and etchants increases the number of processing steps. Moreover, some residual etchants used in etching the polysilicon layer may be carried over into the next etching operation. When they come into contact with the titanium nitride layer, some metallic ion dissociation may occur. Consequently, the reaction chamber may be contaminated.
In light of the foregoing, there is a need to improve the process of etching the polysilicon layer, the titanium nitride layer and the tantalum oxide layer.